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Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
Use 6.8k ? .
C12
C 5 =
2
π × R 3 × f PMOD
=
2
π × 6 . 8 k ? × 17 . 4 kHz
= 5 . 38 nF
C11
R4
Use 4.7nF.
V OUT1
R1
EA
R3
C5
R 1 × R I
R I =
R 3 × f PMOD
f P 2 × G EA ( fZ 1 - fZ 2 )
R 4 = =
R 1 - R I
6 . 8 k ? × 17 . 4 kHz
= = 583 ?
423 kHz × 0 . 479
13 . 3 k ? × 583 ?
= 609 ?
13 . 3 k ? - 583 ?
GAIN
(dB)
R2
V REF
CLOSED-LOOP GAIN
V COMP
Use 620 ? .
EA GAIN
C 11 =
1
2 π × R 4 × f P 2
=
1
2 π × 620 ? × 423 kHz
= 607 pF
Use 680pF.
Pick f P3 = 700kHz, which is the midpoint between f ZESR
f Z1
f Z2
f P2
f C
f P3
FREQUENCY
and 1/2 the switching frequency.
Figure 4. Case 2: Error-Amplifier Compensation Circuit (Closed-
Loop and Error-Amplifier Gain Plot)
C 12 =
C 5
( 2 π × C 5 × R 3 × f P 3 ) -1
The equations that define the error amplifier’s poles
=
Use 33pF.
4 . 7 nF
( 2 π × 4 . 7 nF × 6 . 8 k ? × 700 kHz ) -1
= 33 . 7 pF
and zeroes (f Z1 , f Z2 , f P2 , and f P3 ) are the same as for
Case 1. However, f P2 is now lower than the closed-loop
crossover frequency.
The error-amplifier gain at f C is:
Case 2: Electrolytic Output Capacitor (operating at
lower switching frequencies, f ZESR < f C )
The modulator gain at f C is:
G EA ( fc ) =
1
G MOD ( fc )
f
G EA ( fZ 1 ? fZ 2 ) = G EA ( fc ) Z 2 =
2
G MOD ( fc ) = G MOD ( DC ) PMOD
f ZESR f C
The output capacitor’s ESR zero frequency is higher
than the LC double-pole frequency but lower than the
closed-loop crossover frequency. Here the modulator
already has a -20dB/decade slope; therefore, the error-
amplifier gain must have a 0dB/decade slope at f C , so
the loop crosses over at the desired -20dB/decade
slope. The error-amplifier circuit configuration is the
same as Case 1; however, the closed-loop crossover
frequency is now between f P2 and f P3 , as illustrated in
Figure 4.
And the gain of the error amplifier between f Z1 and
f Z2 is:
f f Z 2
f P 2 f P 2 G MOD ( fc )
Due to the underdamped (Q > 1) nature of the output LC
double pole, the error-amplifier zero frequencies must be
set less than the LC double-pole frequency to provide
adequate phase boost. Set the first zero of the error
amplifier, f Z1 , at 1/4th the LC double-pole frequency. Set
the second zero, f Z2 , at the LC double-pole frequency.
Set the second pole, f P2 , at f ZESR .
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